The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer, such as spin-on-glass (SOG) or high density plasma (HDP) oxide, is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature.
A conventional conductive via is illustrated in FIG. 1, wherein first metal feature 10 of a first patterned metal layer is formed on first dielectric layer 11 and exposed by through-hole 12 formed in second dielectric layer 13. First metal feature 10 comprises side surfaces which taper somewhat due to etching and is typically formed as a composite structure comprising a lower metal layer 10A, e.g., titanium (Ti) or tungsten (W), an intermediate or primary conductive layer 10B, e.g., aluminum (Al) or an Al alloy, and an anti-reflective coating (ARC) 10C, such as titanium nitride (TiN). In accordance with conventional practices, through-hole 12 is formed so that first metal feature 10 encloses the entire bottom opening, thereby serving as a landing pad for the metal plug filling through-hole 12 to form the conductive via. Thus, the entire bottom surface of conductive via 16 is in direct contact with first metal feature 10. Conductive via 16 electrically connects first metal feature 10 and second metal feature 14 which is part of a second patterned metal layer. Second metal feature 14 is also typically formed as a composite structure comprising lower metal layer 14A, primary conductive layer 14B and ARC 14C. The plug filling the through-hole to form the conductive via is typically formed as a composite comprising a first adhesion promoting layer 15, which is typically a refractory material, such as TiN, Ti--W, or Ti--TiN, and a primary plug filling metal 17 such as W. Metal features 10 and 14 typically comprise metal lines with interwiring spacings therebetween conventionally filled with dielectric material 18, such as SOG or HDP oxide.
The reduction in design features to the range of 0.25 microns and under requires extremely high densification which mandates high aspect ratio (height/diameter) openings. As the aspect ratio of openings increases, it becomes increasingly more difficult to deposit a barrier layer 15 (FIG. 1) as by conventional sputtering techniques. It has been recently suggested that chemical vapor deposited (CVD) TiN can be employed to form a conformal coating in a high aspect ratio through-hole, as by the decomposition of an inorganic compound containing Ti, such as tetrakis-dimethylamino titanium (TDMAT). It has also been found that CVD TiN films exhibit a high carbon content and high resistivity. Accordingly, it has also been proposed to treat a deposited CVD TiN film in a hydrogen (H.sub.2)/nitrogen (N.sub.2) plasma to remove carbon and reduce the resistivity of the CVD TiN film. See, for example, A. J. Konecni et al., "A STABLE PLASMA TREATED CVD TITANIUM NITRIDE FILM FOR BARRIER/GLUE LAYER APPLICATIONS," pp. 181-183, Jun. 18-20, 1996, VMIC Conference, 1996 ISMIC; Kim et al., "Stability of TiN Films Prepared by Chemical Vapor Deposition Using Tetrakis-dimethylamino Titanium," J. Electrochem. Soc., Vol. 143, No. 9, September 1996, pp. L188-L190; J. Iacoponi et al., "RESISTIVITY ENHANCEMENT OF CVD TiN WITH IN-SITU NITROGEN PLASMA AND ITS APPLICATION IN LOW RESISTANCE MULTILEVEL INTERCONNECTS," Advanced Metalization and Interconnection Systems for ULSI Applications in 1995; Eizenberg et al., "Chemical vapor deposition TiCN: A new barrier metallization for submicron via and contact applications," J. Vac. Sci. Technol. A 13(3), May/June 1995, pp. 590-595; Eizenberg et al., "TiCN: A new chemical vapor deposited contact barrier metallization for submicron devices," Appl. Phys. Lett., Vol. 65, No. 19, Nov. 7, 1994, pp. 2416-2418; and Hillman et al., "COMPARISON OF TITANIUM NITRIDE BARRIER LAYERS PRODUCED BY INORGANIC AND ORGANIC CVD," pp. 246-252, Jun. 9-10, 1992, VMIC Conference, 1992 ISMIC.
The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high densification requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, e.g., in excess of 4. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a "borderless via", which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated by etching when forming a through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture and gas accumulate thereby increasing the resistance of the interconnection. Moreover, spiking can occur, i.e., penetration of the metal plug to the substrate causing a short.
In copending application Ser. No. 08/924,133, filed on Sep. 5, 1997, a method is disclosed comprising gap filling with HDP oxide deposited by high density plasma chemical vapor deposition (HDP-CVD), wherein annealing is performed in order to increase the grain size and, consequentially, improve the electromigration resistance of the patterned metal layers.
However, the use of borderless vias is also problematic in that a side surface of a metal feature is exposed to etching during formation of the through-hole, resulting in the undesirable formation of an etched undercut portion of a side surface of the metal feature. Adverting to FIG. 2, first metal feature 20 is formed on first insulating layer 21. First metal feature 20 is part of a first patterned metal layer comprising a first lower metal layer 20A, a primary intermediate metal layer 20B, such as Al or an Al alloy, and an upper ARC 20C. A second dielectric layer 22 is formed on the first patterned metal layer and through-hole 23 etched therein, which through-hole is purposely misaligned, thereby exposing a portion 24 of the upper surface of first metal feature 20 and undercutting a portion of a side surface of metal feature 20 to form an etched undercut portion 25 in the form of a concavity extending under but not including ARC 20C. The difficulty of filling a borderless via having a high aspect ratio is exacerbated by the even higher aspect ratio of the portion of the borderless via adjacent the etched undercut portion 25 on the side surface of first metal feature 20. The difficulty in depositing a barrier material on undercut concave portion 25 becomes acutely problematic.
In depositing W from tungsten hexafluoride (WF.sub.6) vapor, it is recognized that an interaction with Al occurs. Accordingly, as depicted in FIG. 1, conventional practices comprise depositing a barrier layer 15, such as TiN, by sputtering. However, it is extremely difficult to sputter TiN in a through-hole having a high aspect ratio, let alone to coat concave undercut portion on the side surface of a lower metal feature in the offset region. Accordingly, there exists a need for a methodology enabling the formation of a TiN barrier layer on an undercut side surface of a lower metal feature for electrical connection to an upper metal feature by a borderless via.